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Rev Log message Author Age Path
365 Whitespace cleanup olof 4971d 06h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4972d 04h /
363 quartus project files unneback 4972d 12h /
362 added Makefiles to build project unneback 4972d 12h /
361 created branch unneback unneback 4972d 13h /
360 Added partial implementation of the debug register from ORPSoC olof 4973d 11h /
359 Verilator linting fixes olof 4975d 13h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4977d 03h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4977d 04h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4977d 05h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4977d 06h /
354 Whitespace cleanup olof 4977d 07h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4979d 08h /
352 Removed delayed assignments from rtl code olof 4983d 14h /
351 Turn defines into parameters in eth_cop olof 4992d 04h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4992d 04h /
349 Make all parameters configurable from top level olof 4993d 05h /
348 Added option to dump VCD files olof 4994d 04h /
347 Added information about running with Icarus Verilog olof 4994d 05h /
346 Updated project location olof 4994d 07h /
345 Temporarily disable failing tests olof 4994d 08h /
344 bit 9 in phy control register is self clearing olof 5000d 10h /
343 Address miss should not be asserted on short frames olof 5004d 06h /
342 Added cast to avoid inequality when comparing different data types olof 5004d 06h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 5004d 07h /
340 Don't fail if log dir already exists olof 5005d 04h /
339 Added basic support for Icarus Verilog olof 5006d 03h /
338 root 5798d 09h /
337 root 5854d 11h /
336 Added old uploaded documents to new repository. root 5855d 14h /

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