OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 368

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2852d 16h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2915d 14h /
366 Readded eth_top.v with a deprecation warning olof 3039d 18h /
365 Whitespace cleanup olof 3040d 17h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3041d 14h /
363 quartus project files unneback 3041d 23h /
362 added Makefiles to build project unneback 3041d 23h /
361 created branch unneback unneback 3041d 23h /
360 Added partial implementation of the debug register from ORPSoC olof 3042d 22h /
359 Verilator linting fixes olof 3045d 00h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3046d 14h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3046d 14h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3046d 16h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3046d 17h /
354 Whitespace cleanup olof 3046d 17h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3048d 19h /
352 Removed delayed assignments from rtl code olof 3053d 01h /
351 Turn defines into parameters in eth_cop olof 3061d 15h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3061d 15h /
349 Make all parameters configurable from top level olof 3062d 16h /
348 Added option to dump VCD files olof 3063d 15h /
347 Added information about running with Icarus Verilog olof 3063d 15h /
346 Updated project location olof 3063d 17h /
345 Temporarily disable failing tests olof 3063d 19h /
344 bit 9 in phy control register is self clearing olof 3069d 21h /
343 Address miss should not be asserted on short frames olof 3073d 17h /
342 Added cast to avoid inequality when comparing different data types olof 3073d 17h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3073d 17h /
340 Don't fail if log dir already exists olof 3074d 15h /
339 Added basic support for Icarus Verilog olof 3075d 14h /

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.