OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 368

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 4453d 13h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4516d 10h /
366 Readded eth_top.v with a deprecation warning olof 4640d 14h /
365 Whitespace cleanup olof 4641d 13h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4642d 11h /
363 quartus project files unneback 4642d 20h /
362 added Makefiles to build project unneback 4642d 20h /
361 created branch unneback unneback 4642d 20h /
360 Added partial implementation of the debug register from ORPSoC olof 4643d 19h /
359 Verilator linting fixes olof 4645d 21h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4647d 11h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4647d 11h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4647d 13h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4647d 14h /
354 Whitespace cleanup olof 4647d 14h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4649d 15h /
352 Removed delayed assignments from rtl code olof 4653d 21h /
351 Turn defines into parameters in eth_cop olof 4662d 11h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4662d 12h /
349 Make all parameters configurable from top level olof 4663d 12h /
348 Added option to dump VCD files olof 4664d 11h /
347 Added information about running with Icarus Verilog olof 4664d 12h /
346 Updated project location olof 4664d 14h /
345 Temporarily disable failing tests olof 4664d 16h /
344 bit 9 in phy control register is self clearing olof 4670d 18h /
343 Address miss should not be asserted on short frames olof 4674d 14h /
342 Added cast to avoid inequality when comparing different data types olof 4674d 14h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4674d 14h /
340 Don't fail if log dir already exists olof 4675d 11h /
339 Added basic support for Icarus Verilog olof 4676d 11h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.