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Rev	Log message	Author	Age	Path
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8112d 06h	/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8121d 08h	/
37	Link in the header changed.	mohor	8121d 08h	/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8167d 06h	/
35	RX_BD_NUM changed to TX_BD_NUM. Few typos corrected.	mohor	8170d 03h	/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8170d 04h	/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8170d 08h	/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8170d 08h	/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8170d 09h	/
30	BD section updated.	mohor	8172d 05h	/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8192d 04h	/
28	New release. Name changed to lower case.	mohor	8194d 20h	/
27	File names changed to lower case.	mohor	8194d 20h	/
26	First release of product brief.	mohor	8194d 20h	/
25	First release of product brief.	mohor	8194d 20h	/
24	Log file added.	mohor	8217d 07h	/
23	Number of addresses (wb_adr_i) minimized.	mohor	8217d 07h	/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8217d 10h	/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8218d 06h	/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8242d 03h	/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8242d 04h	/
18	Few little NCSIM warnings fixed.	mohor	8255d 04h	/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8282d 04h	/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8289d 10h	/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8291d 04h	/
14	Unconnected signals are now connected.	mohor	8295d 09h	/
13	New directory structure. Files upodated and put together.	mohor	8297d 18h	/
12	Directory structure changed. Files checked and joind together.	mohor	8297d 21h	/
11	Directory structure changed. Files checked and joind together.	mohor	8297d 21h	/
10	Directory structure changed. Files checked and joind together.	mohor	8297d 21h	/

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[/] - Rev 39

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