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Rev Log message Author Age Path
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8112d 05h /
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8113d 03h /
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8117d 06h /
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8126d 08h /
37 Link in the header changed. mohor 8126d 09h /
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8172d 07h /
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8175d 04h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8175d 04h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8175d 08h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8175d 09h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8175d 09h /
30 BD section updated. mohor 8177d 06h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 8197d 05h /
28 New release. Name changed to lower case. mohor 8199d 20h /
27 File names changed to lower case. mohor 8199d 20h /
26 First release of product brief. mohor 8199d 21h /
25 First release of product brief. mohor 8199d 21h /
24 Log file added. mohor 8222d 08h /
23 Number of addresses (wb_adr_i) minimized. mohor 8222d 08h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8222d 10h /

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