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Rev Log message Author Age Path
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8082d 06h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8082d 07h /
80 Small fixes for external/internal DMA missmatches. mohor 8086d 09h /
79 RetryCntLatched was unused and removed from design mohor 8086d 09h /
78 WB_SEL_I was unused and removed from design mohor 8086d 09h /
77 Interrupts changed mohor 8086d 09h /
76 Interrupts changed in the top file mohor 8086d 09h /
75 r_Bro is used for accepting/denying frames mohor 8086d 09h /
74 Reset values are passed to registers through parameters mohor 8086d 09h /
73 Number of interrupts changed mohor 8086d 09h /
72 Retry is not activated when a Tx Underrun occured mohor 8090d 13h /
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.
mohor 8094d 14h /
70 Small fixes. mohor 8094d 15h /
69 Define missmatch fixed. mohor 8095d 12h /
68 Registered trimmed. Unused registers removed. mohor 8096d 12h /
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8096d 13h /
66 Testbench fixed, code simplified, unused signals removed. mohor 8096d 18h /
65 Testbench fixed, code simplified, unused signals removed. mohor 8096d 18h /
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8097d 09h /
63 RxAbort is connected differently. mohor 8097d 12h /

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