OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 98

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Document revised. mohor 7169d 03h /
97 Small typo fixed. lampret 7186d 02h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7190d 02h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7190d 05h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7190d 05h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 7195d 03h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 7196d 05h /
91 Comments in Slovene language removed. mohor 7196d 05h /
90 casex changed with case, fifo reset changed. mohor 7196d 05h /
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.
mohor 7200d 03h /
88 rx_fifo was not always cleared ok. Fixed. mohor 7206d 02h /
87 Status was not latched correctly sometimes. Fixed. mohor 7206d 04h /
86 Big Endian problem when sending frames fixed. mohor 7207d 11h /
85 Log info was missing. mohor 7212d 21h /
84 LinkFail signal was not latching appropriate bit. mohor 7212d 21h /
83 MAC address recognition was not correct (bytes swaped). mohor 7212d 21h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 7212d 23h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 7212d 23h /
80 Small fixes for external/internal DMA missmatches. mohor 7217d 01h /
79 RetryCntLatched was unused and removed from design mohor 7217d 02h /
78 WB_SEL_I was unused and removed from design mohor 7217d 02h /
77 Interrupts changed mohor 7217d 02h /
76 Interrupts changed in the top file mohor 7217d 02h /
75 r_Bro is used for accepting/denying frames mohor 7217d 02h /
74 Reset values are passed to registers through parameters mohor 7217d 02h /
73 Number of interrupts changed mohor 7217d 02h /
72 Retry is not activated when a Tx Underrun occured mohor 7221d 05h /
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.
mohor 7225d 06h /
70 Small fixes. mohor 7225d 07h /
69 Define missmatch fixed. mohor 7226d 05h /

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.