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Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3829d 00h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3829d 00h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3829d 02h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3829d 02h /ethmac/
354 Whitespace cleanup olof 3829d 03h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 3831d 04h /ethmac/
352 Removed delayed assignments from rtl code olof 3835d 10h /ethmac/
351 Turn defines into parameters in eth_cop olof 3844d 00h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3844d 01h /ethmac/
349 Make all parameters configurable from top level olof 3845d 01h /ethmac/
348 Added option to dump VCD files olof 3846d 00h /ethmac/
347 Added information about running with Icarus Verilog olof 3846d 01h /ethmac/
346 Updated project location olof 3846d 03h /ethmac/
345 Temporarily disable failing tests olof 3846d 05h /ethmac/
344 bit 9 in phy control register is self clearing olof 3852d 07h /ethmac/
343 Address miss should not be asserted on short frames olof 3856d 03h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 3856d 03h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3856d 03h /ethmac/
340 Don't fail if log dir already exists olof 3857d 00h /ethmac/
339 Added basic support for Icarus Verilog olof 3858d 00h /ethmac/
338 root 4650d 05h /ethmac/
337 root 4706d 07h /ethernet/
336 Added old uploaded documents to new repository. root 4707d 11h /ethernet/
335 New directory structure. root 4707d 11h /ethernet/

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