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Rev Log message Author Age Path
363 quartus project files unneback 3934d 11h /ethmac
362 added Makefiles to build project unneback 3934d 12h /ethmac
361 created branch unneback unneback 3934d 12h /ethmac
360 Added partial implementation of the debug register from ORPSoC olof 3935d 10h /ethmac
359 Verilator linting fixes olof 3937d 13h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3939d 03h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3939d 03h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3939d 05h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 3939d 05h /ethmac
354 Whitespace cleanup olof 3939d 06h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 3941d 07h /ethmac
352 Removed delayed assignments from rtl code olof 3945d 13h /ethmac
351 Turn defines into parameters in eth_cop olof 3954d 03h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3954d 04h /ethmac
349 Make all parameters configurable from top level olof 3955d 04h /ethmac
348 Added option to dump VCD files olof 3956d 03h /ethmac
347 Added information about running with Icarus Verilog olof 3956d 04h /ethmac
346 Updated project location olof 3956d 06h /ethmac
345 Temporarily disable failing tests olof 3956d 07h /ethmac
344 bit 9 in phy control register is self clearing olof 3962d 10h /ethmac

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