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Rev Log message Author Age Path
361 created branch unneback unneback 4437d 16h /ethmac/branches/unneback/
352 Removed delayed assignments from rtl code olof 4448d 17h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 4457d 07h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4457d 07h /ethmac/trunk/
349 Make all parameters configurable from top level olof 4458d 08h /ethmac/trunk/
348 Added option to dump VCD files olof 4459d 07h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 4459d 08h /ethmac/trunk/
346 Updated project location olof 4459d 10h /ethmac/trunk/
345 Temporarily disable failing tests olof 4459d 11h /ethmac/trunk/
344 bit 9 in phy control register is self clearing olof 4465d 13h /ethmac/trunk/
343 Address miss should not be asserted on short frames olof 4469d 09h /ethmac/trunk/
342 Added cast to avoid inequality when comparing different data types olof 4469d 10h /ethmac/trunk/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4469d 10h /ethmac/trunk/
340 Don't fail if log dir already exists olof 4470d 07h /ethmac/trunk/
339 Added basic support for Icarus Verilog olof 4471d 07h /ethmac/trunk/
338 root 5263d 12h /ethmac/trunk/
335 New directory structure. root 5320d 17h /ethernet/trunk/
334 Minor fixes for Icarus simulator. igorm 6768d 20h /trunk/
333 Some small fixes + some troubles fixed. igorm 6769d 07h /trunk/
332 Case statement improved for synthesys. igorm 6782d 13h /trunk/

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