OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 363

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
363 quartus project files unneback 4816d 19h /ethmac/branches/unneback/rtl/verilog/
362 added Makefiles to build project unneback 4816d 20h /ethmac/branches/unneback/rtl/verilog/
361 created branch unneback unneback 4816d 20h /ethmac/branches/unneback/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4827d 21h /ethmac/branches/unneback/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4836d 11h /ethmac/branches/unneback/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4836d 12h /ethmac/branches/unneback/rtl/verilog/
349 Make all parameters configurable from top level olof 4837d 12h /ethmac/branches/unneback/rtl/verilog/
346 Updated project location olof 4838d 14h /ethmac/branches/unneback/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4848d 14h /ethmac/branches/unneback/rtl/verilog/
338 root 5642d 16h /ethmac/branches/unneback/rtl/verilog/
335 New directory structure. root 5699d 21h /ethmac/branches/unneback/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7148d 11h /ethmac/branches/unneback/rtl/verilog/
332 Case statement improved for synthesys. igorm 7161d 17h /ethmac/branches/unneback/rtl/verilog/
330 Warning fixes. igorm 7176d 19h /ethmac/branches/unneback/rtl/verilog/
329 Defer indication fixed. igorm 7176d 20h /ethmac/branches/unneback/rtl/verilog/
328 Delayed CRC fixed. igorm 7176d 20h /ethmac/branches/unneback/rtl/verilog/
327 Defer indication fixed. igorm 7176d 20h /ethmac/branches/unneback/rtl/verilog/
326 Delayed CRC fixed. igorm 7176d 21h /ethmac/branches/unneback/rtl/verilog/
325 Defer indication fixed. igorm 7176d 21h /ethmac/branches/unneback/rtl/verilog/
323 Accidently deleted line put back. igorm 7473d 21h /ethmac/branches/unneback/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.