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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 280

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Rev Log message Author Age Path
280 Reset has priority in some flipflops. mohor 7728d 04h /ethmac/branches/unneback/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7728d 05h /ethmac/branches/unneback/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7728d 05h /ethmac/branches/unneback/rtl/verilog/
276 Defer indication changed. tadejm 7728d 05h /ethmac/branches/unneback/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7735d 09h /ethmac/branches/unneback/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7736d 05h /ethmac/branches/unneback/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7737d 06h /ethmac/branches/unneback/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7738d 06h /ethmac/branches/unneback/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7797d 05h /ethmac/branches/unneback/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7797d 16h /ethmac/branches/unneback/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7798d 18h /ethmac/branches/unneback/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7798d 18h /ethmac/branches/unneback/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7798d 18h /ethmac/branches/unneback/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7798d 18h /ethmac/branches/unneback/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7800d 00h /ethmac/branches/unneback/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7800d 01h /ethmac/branches/unneback/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7800d 01h /ethmac/branches/unneback/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7801d 01h /ethmac/branches/unneback/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7804d 04h /ethmac/branches/unneback/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7805d 00h /ethmac/branches/unneback/rtl/verilog/

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