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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 362


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Rev Log message Author Age Path
362 added Makefiles to build project unneback 4725d 00h /ethmac/branches/unneback/rtl/verilog/
361 created branch unneback unneback 4725d 00h /ethmac/branches/unneback/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4736d 01h /ethmac/branches/unneback/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4744d 15h /ethmac/branches/unneback/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4744d 16h /ethmac/branches/unneback/rtl/verilog/
349 Make all parameters configurable from top level olof 4745d 16h /ethmac/branches/unneback/rtl/verilog/
346 Updated project location olof 4746d 18h /ethmac/branches/unneback/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4756d 18h /ethmac/branches/unneback/rtl/verilog/
338 root 5550d 20h /ethmac/branches/unneback/rtl/verilog/
335 New directory structure. root 5608d 02h /ethmac/branches/unneback/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7056d 16h /ethmac/branches/unneback/rtl/verilog/
332 Case statement improved for synthesys. igorm 7069d 21h /ethmac/branches/unneback/rtl/verilog/
330 Warning fixes. igorm 7084d 23h /ethmac/branches/unneback/rtl/verilog/
329 Defer indication fixed. igorm 7085d 00h /ethmac/branches/unneback/rtl/verilog/
328 Delayed CRC fixed. igorm 7085d 00h /ethmac/branches/unneback/rtl/verilog/
327 Defer indication fixed. igorm 7085d 01h /ethmac/branches/unneback/rtl/verilog/
326 Delayed CRC fixed. igorm 7085d 01h /ethmac/branches/unneback/rtl/verilog/
325 Defer indication fixed. igorm 7085d 01h /ethmac/branches/unneback/rtl/verilog/
323 Accidently deleted line put back. igorm 7382d 01h /ethmac/branches/unneback/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7385d 20h /ethmac/branches/unneback/rtl/verilog/

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