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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 362

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Rev Log message Author Age Path
362 added Makefiles to build project unneback 3397d 20h /ethmac/branches/unneback/rtl/verilog/
361 created branch unneback unneback 3397d 21h /ethmac/branches/unneback/rtl/verilog/
352 Removed delayed assignments from rtl code olof 3408d 22h /ethmac/branches/unneback/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 3417d 12h /ethmac/branches/unneback/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3417d 12h /ethmac/branches/unneback/rtl/verilog/
349 Make all parameters configurable from top level olof 3418d 13h /ethmac/branches/unneback/rtl/verilog/
346 Updated project location olof 3419d 15h /ethmac/branches/unneback/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3429d 15h /ethmac/branches/unneback/rtl/verilog/
338 root 4223d 17h /ethmac/branches/unneback/rtl/verilog/
335 New directory structure. root 4280d 22h /ethmac/branches/unneback/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 5729d 12h /ethmac/branches/unneback/rtl/verilog/
332 Case statement improved for synthesys. igorm 5742d 18h /ethmac/branches/unneback/rtl/verilog/
330 Warning fixes. igorm 5757d 20h /ethmac/branches/unneback/rtl/verilog/
329 Defer indication fixed. igorm 5757d 21h /ethmac/branches/unneback/rtl/verilog/
328 Delayed CRC fixed. igorm 5757d 21h /ethmac/branches/unneback/rtl/verilog/
327 Defer indication fixed. igorm 5757d 21h /ethmac/branches/unneback/rtl/verilog/
326 Delayed CRC fixed. igorm 5757d 21h /ethmac/branches/unneback/rtl/verilog/
325 Defer indication fixed. igorm 5757d 22h /ethmac/branches/unneback/rtl/verilog/
323 Accidently deleted line put back. igorm 6054d 22h /ethmac/branches/unneback/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6058d 17h /ethmac/branches/unneback/rtl/verilog/

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