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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_cop.v] - Rev 362

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361 created branch unneback unneback 3399d 20h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
352 Removed delayed assignments from rtl code olof 3410d 22h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
351 Turn defines into parameters in eth_cop olof 3419d 11h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3419d 12h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
346 Updated project location olof 3421d 14h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
338 root 4225d 17h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
335 New directory structure. root 4282d 22h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6378d 20h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
212 Minor $display change. mohor 6624d 15h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
160 error acknowledge cycle termination added to display. mohor 6655d 19h /ethmac/branches/unneback/rtl/verilog/eth_cop.v
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6681d 15h /ethmac/branches/unneback/rtl/verilog/eth_cop.v

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