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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_defines.v] - Rev 362

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4634d 05h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
351	Turn defines into parameters in eth_cop	olof	4653d 21h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4653d 21h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
346	Updated project location	olof	4656d 00h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
338		root	5460d 02h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
335	New directory structure.	root	5517d 07h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
330	Warning fixes.	igorm	6994d 04h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7460d 23h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
302	mbist signals updated according to newest convention	markom	7487d 09h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
297	Artisan ram instance added.	simons	7551d 00h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7613d 05h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7818d 23h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7823d 03h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
238	Defines fixed to use generic RAM by default.	mohor	7836d 23h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
232	fpga define added.	mohor	7844d 22h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7859d 00h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
211	Bist added.	mohor	7859d 01h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7875d 23h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7894d 23h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7913d 19h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7915d 22h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7938d 02h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8019d 07h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8028d 08h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8064d 04h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
73	Number of interrupts changed	mohor	8085d 01h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8095d 03h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8095d 04h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
55	Changed that were lost with last update put back to the file.	mohor	8096d 06h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8096d 21h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_defines.v] - Rev 362

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