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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 362

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244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7805d 04h /ethmac/branches/unneback/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7806d 01h /ethmac/branches/unneback/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7832d 06h /ethmac/branches/unneback/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7839d 09h /ethmac/branches/unneback/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7840d 06h /ethmac/branches/unneback/rtl/verilog/eth_top.v
210 BIST added. mohor 7840d 06h /ethmac/branches/unneback/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7860d 06h /ethmac/branches/unneback/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7868d 08h /ethmac/branches/unneback/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7870d 12h /ethmac/branches/unneback/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7871d 10h /ethmac/branches/unneback/rtl/verilog/eth_top.v

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