OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 349

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
349 Make all parameters configurable from top level olof 4636d 20h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
346 Updated project location olof 4637d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
338 root 5442d 00h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
335 New directory structure. root 5499d 05h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
333 Some small fixes + some troubles fixed. igorm 6947d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
329 Defer indication fixed. igorm 6976d 04h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
323 Accidently deleted line put back. igorm 7273d 05h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7277d 00h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7442d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
302 mbist signals updated according to newest convention markom 7469d 08h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 7729d 01h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7729d 02h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 7737d 02h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7738d 03h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7739d 03h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7798d 02h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7798d 13h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7800d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7806d 17h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7832d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.