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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 362


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361 created branch unneback unneback 3397d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
352 Removed delayed assignments from rtl code olof 3408d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
349 Make all parameters configurable from top level olof 3418d 13h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
346 Updated project location olof 3419d 15h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
338 root 4223d 17h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
335 New directory structure. root 4280d 23h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
333 Some small fixes + some troubles fixed. igorm 5729d 12h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
329 Defer indication fixed. igorm 5757d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
323 Accidently deleted line put back. igorm 6054d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6058d 17h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6224d 14h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
302 mbist signals updated according to newest convention markom 6251d 01h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 6510d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 6510d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 6518d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6519d 20h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6520d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6579d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 6580d 07h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6582d 15h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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