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Rev Log message Author Age Path
177 Bug in MIIM fixed. mohor 7280d 08h /ethmac/tags/asyst_2/
176 lists changed to new directory structure mohor 7280d 09h /ethmac/tags/asyst_2/
175 Script fixed to new dir structure mohor 7280d 09h /ethmac/tags/asyst_2/
174 Directory keeper mohor 7280d 09h /ethmac/tags/asyst_2/
173 Keeps the directory mohor 7280d 09h /ethmac/tags/asyst_2/
172 NCSIM simulation environment added to cvs mohor 7280d 10h /ethmac/tags/asyst_2/
171 NCSIM simulation environment added. mohor 7280d 10h /ethmac/tags/asyst_2/
170 Headers changed. mohor 7280d 10h /ethmac/tags/asyst_2/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7280d 11h /ethmac/tags/asyst_2/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7281d 08h /ethmac/tags/asyst_2/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7282d 08h /ethmac/tags/asyst_2/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7283d 09h /ethmac/tags/asyst_2/
165 HASH improvement needed. mohor 7283d 12h /ethmac/tags/asyst_2/
164 Ethernet debug registers removed. mohor 7283d 12h /ethmac/tags/asyst_2/
163 Another temporary version. Core is almost finished. Testbench not included,
mohor 7284d 04h /ethmac/tags/asyst_2/
162 Another temporary version. Core is almost finished. Testbench not included,
mohor 7284d 04h /ethmac/tags/asyst_2/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7284d 09h /ethmac/tags/asyst_2/
160 error acknowledge cycle termination added to display. mohor 7284d 10h /ethmac/tags/asyst_2/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7285d 06h /ethmac/tags/asyst_2/
158 Typo fixed. mohor 7285d 06h /ethmac/tags/asyst_2/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7287d 11h /ethmac/tags/asyst_2/
156 Valid testbench. mohor 7287d 11h /ethmac/tags/asyst_2/
155 Minor changes. mohor 7287d 12h /ethmac/tags/asyst_2/
154 Design document is still under construction. mohor 7288d 11h /ethmac/tags/asyst_2/
153 Temp version (backup). mohor 7289d 02h /ethmac/tags/asyst_2/
152 Version 1.16 created. See revision history in the document for details. mohor 7289d 02h /ethmac/tags/asyst_2/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7289d 04h /ethmac/tags/asyst_2/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
mohor 7289d 04h /ethmac/tags/asyst_2/
148 Bug when last byte of destination address was not checked fixed. mohor 7289d 04h /ethmac/tags/asyst_2/
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7289d 04h /ethmac/tags/asyst_2/

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