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[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 338

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Rev Log message Author Age Path
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7758d 19h /ethmac/tags/asyst_2/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7759d 20h /ethmac/tags/asyst_2/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7818d 18h /ethmac/tags/asyst_2/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7819d 06h /ethmac/tags/asyst_2/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7820d 07h /ethmac/tags/asyst_2/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7820d 07h /ethmac/tags/asyst_2/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7820d 07h /ethmac/tags/asyst_2/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7820d 07h /ethmac/tags/asyst_2/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7821d 13h /ethmac/tags/asyst_2/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7821d 14h /ethmac/tags/asyst_2/rtl/verilog/

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