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[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] [eth_cop.v] - Rev 338

Rev	Log message	Author	Age	Path
338		root	5467d 11h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v
335	New directory structure.	root	5524d 16h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v
313	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7445d 14h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7620d 14h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v
212	Minor $display change.	mohor	7866d 10h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v
160	error acknowledge cycle termination added to display.	mohor	7897d 13h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7923d 09h	/ethmac/tags/asyst_2/rtl/verilog/eth_cop.v