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[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] [eth_top.v] - Rev 338

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Rev Log message Author Age Path
338 root 5462d 23h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
335 New directory structure. root 5520d 04h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
313 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7441d 02h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7463d 20h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
302 mbist signals updated according to newest convention markom 7490d 07h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7500d 23h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 7750d 01h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 7758d 00h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7759d 02h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7819d 12h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 7820d 14h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7821d 20h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7821d 21h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 7822d 21h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7826d 20h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7827d 16h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7853d 21h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7861d 01h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7861d 21h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v
210 BIST added. mohor 7861d 22h /ethmac/tags/asyst_2/rtl/verilog/eth_top.v

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