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Rev Log message Author Age Path
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8036d 19h /ethmac/tags/rel_1/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8036d 19h /ethmac/tags/rel_1/
99 Document revised. mohor 8043d 18h /ethmac/tags/rel_1/
98 Document revised. mohor 8043d 18h /ethmac/tags/rel_1/
97 Small typo fixed. lampret 8060d 16h /ethmac/tags/rel_1/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8064d 16h /ethmac/tags/rel_1/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8064d 19h /ethmac/tags/rel_1/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8064d 19h /ethmac/tags/rel_1/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8069d 17h /ethmac/tags/rel_1/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8070d 20h /ethmac/tags/rel_1/
91 Comments in Slovene language removed. mohor 8070d 20h /ethmac/tags/rel_1/
90 casex changed with case, fifo reset changed. mohor 8070d 20h /ethmac/tags/rel_1/
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.		 mohor 8074d 18h /ethmac/tags/rel_1/
88 rx_fifo was not always cleared ok. Fixed. mohor 8080d 16h /ethmac/tags/rel_1/
87 Status was not latched correctly sometimes. Fixed. mohor 8080d 19h /ethmac/tags/rel_1/
86 Big Endian problem when sending frames fixed. mohor 8082d 02h /ethmac/tags/rel_1/
85 Log info was missing. mohor 8087d 11h /ethmac/tags/rel_1/
84 LinkFail signal was not latching appropriate bit. mohor 8087d 11h /ethmac/tags/rel_1/
83 MAC address recognition was not correct (bytes swaped). mohor 8087d 12h /ethmac/tags/rel_1/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8087d 13h /ethmac/tags/rel_1/

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