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[/] [ethmac/] [tags/] [rel_1/] [rtl/] - Rev 358

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Rev Log message Author Age Path
338 root 5459d 15h /ethmac/tags/rel_1/rtl
335 New directory structure. root 5516d 20h /ethmac/tags/rel_1/rtl
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7937d 14h /ethmac/tags/rel_1/rtl
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7937d 14h /ethmac/tags/rel_1/rtl
120 Unused files removed. mohor 7937d 15h /ethmac/tags/rel_1/rtl
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7937d 15h /ethmac/tags/rel_1/rtl
118 ShiftEnded synchronization changed. mohor 7941d 06h /ethmac/tags/rel_1/rtl
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7942d 14h /ethmac/tags/rel_1/rtl
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7943d 11h /ethmac/tags/rel_1/rtl
113 RxPointer bug fixed. mohor 7950d 03h /ethmac/tags/rel_1/rtl
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7950d 17h /ethmac/tags/rel_1/rtl
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7951d 06h /ethmac/tags/rel_1/rtl
110 m_wb_cyc_o signal released after every single transfer. mohor 7951d 10h /ethmac/tags/rel_1/rtl
109 Comment removed. mohor 7951d 10h /ethmac/tags/rel_1/rtl
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8018d 20h /ethmac/tags/rel_1/rtl
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8027d 21h /ethmac/tags/rel_1/rtl
104 FCS should not be included in NibbleMinFl. mohor 8029d 15h /ethmac/tags/rel_1/rtl
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8029d 16h /ethmac/tags/rel_1/rtl
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8029d 16h /ethmac/tags/rel_1/rtl
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8029d 16h /ethmac/tags/rel_1/rtl

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