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Rev Log message Author Age Path
214 Signals for WISHBONE B3 compliant interface added. mohor 6866d 09h /ethmac/tags/rel_10/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6866d 09h /ethmac/tags/rel_10/
212 Minor $display change. mohor 6866d 09h /ethmac/tags/rel_10/
211 Bist added. mohor 6866d 09h /ethmac/tags/rel_10/
210 BIST added. mohor 6866d 09h /ethmac/tags/rel_10/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6867d 12h /ethmac/tags/rel_10/
208 Virtual Silicon RAMs moved to lib directory tadej 6883d 06h /ethmac/tags/rel_10/
207 Virtual Silicon RAM support fixed tadej 6883d 06h /ethmac/tags/rel_10/
206 Virtual Silicon RAM added to the simulation. mohor 6883d 07h /ethmac/tags/rel_10/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6883d 07h /ethmac/tags/rel_10/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6883d 07h /ethmac/tags/rel_10/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6883d 07h /ethmac/tags/rel_10/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6886d 09h /ethmac/tags/rel_10/
201 Core size added to the document. mohor 6886d 09h /ethmac/tags/rel_10/
200 File with lower case checked in instead. mohor 6886d 09h /ethmac/tags/rel_10/
199 Datasheet name changed to lower case name. mohor 6886d 09h /ethmac/tags/rel_10/
198 Removed file. File with name in lower case will be added instead. mohor 6886d 09h /ethmac/tags/rel_10/
197 Ethernet Data Sheet. mohor 6886d 09h /ethmac/tags/rel_10/
196 Ethernet product brief. mohor 6886d 11h /ethmac/tags/rel_10/
195 Product brief removed because it is the same as Datasheet. mohor 6886d 11h /ethmac/tags/rel_10/

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