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Rev Log message Author Age Path
338 root 4195d 01h /ethmac/tags/rel_10/
335 New directory structure. root 4252d 06h /ethmac/tags/rel_10/
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6558d 02h /ethmac/tags/rel_10/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6558d 02h /ethmac/tags/rel_10/
245 Rev 1.7. mohor 6558d 19h /ethmac/tags/rel_10/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6558d 21h /ethmac/tags/rel_10/
243 Late collision is not reported any more. tadejm 6559d 03h /ethmac/tags/rel_10/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6559d 18h /ethmac/tags/rel_10/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6559d 18h /ethmac/tags/rel_10/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6559d 18h /ethmac/tags/rel_10/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6559d 18h /ethmac/tags/rel_10/
238 Defines fixed to use generic RAM by default. mohor 6571d 22h /ethmac/tags/rel_10/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6574d 03h /ethmac/tags/rel_10/
235 rev 4. mohor 6574d 18h /ethmac/tags/rel_10/
234 Figure list assed to the revision 3. mohor 6575d 02h /ethmac/tags/rel_10/
233 Revision 0.3 released. Some figures added. mohor 6575d 02h /ethmac/tags/rel_10/
232 fpga define added. mohor 6579d 21h /ethmac/tags/rel_10/
231 Description of Core Modules added (figure). mohor 6581d 22h /ethmac/tags/rel_10/
229 case changed to casex. mohor 6585d 19h /ethmac/tags/rel_10/
227 Changed BIST scan signals. tadejm 6585d 23h /ethmac/tags/rel_10/

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