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Rev Log message Author Age Path
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6569d 04h /ethmac/tags/rel_11/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6570d 01h /ethmac/tags/rel_11/
113 RxPointer bug fixed. mohor 6576d 17h /ethmac/tags/rel_11/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6577d 07h /ethmac/tags/rel_11/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6577d 20h /ethmac/tags/rel_11/
110 m_wb_cyc_o signal released after every single transfer. mohor 6577d 23h /ethmac/tags/rel_11/
109 Comment removed. mohor 6578d 00h /ethmac/tags/rel_11/
108 Testbench supports unaligned accesses. mohor 6645d 10h /ethmac/tags/rel_11/
107 TX_BUF_BASE changed. mohor 6645d 10h /ethmac/tags/rel_11/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6645d 10h /ethmac/tags/rel_11/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6654d 11h /ethmac/tags/rel_11/
104 FCS should not be included in NibbleMinFl. mohor 6656d 05h /ethmac/tags/rel_11/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6656d 06h /ethmac/tags/rel_11/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6656d 06h /ethmac/tags/rel_11/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6656d 06h /ethmac/tags/rel_11/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6656d 06h /ethmac/tags/rel_11/
99 Document revised. mohor 6663d 05h /ethmac/tags/rel_11/
98 Document revised. mohor 6663d 05h /ethmac/tags/rel_11/
97 Small typo fixed. lampret 6680d 04h /ethmac/tags/rel_11/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 6684d 04h /ethmac/tags/rel_11/

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