OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_11/] - Rev 236

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7842d 01h /ethmac/tags/rel_11/
235 rev 4. mohor 7842d 15h /ethmac/tags/rel_11/
234 Figure list assed to the revision 3. mohor 7842d 23h /ethmac/tags/rel_11/
233 Revision 0.3 released. Some figures added. mohor 7843d 00h /ethmac/tags/rel_11/
232 fpga define added. mohor 7847d 19h /ethmac/tags/rel_11/
231 Description of Core Modules added (figure). mohor 7849d 20h /ethmac/tags/rel_11/
229 case changed to casex. mohor 7853d 17h /ethmac/tags/rel_11/
227 Changed BIST scan signals. tadejm 7853d 20h /ethmac/tags/rel_11/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7853d 22h /ethmac/tags/rel_11/
225 Some minor changes. tadejm 7853d 22h /ethmac/tags/rel_11/
224 Signals for a wave window in Modelsim. tadejm 7853d 23h /ethmac/tags/rel_11/
223 Some code changed due to bug fixes. tadejm 7853d 23h /ethmac/tags/rel_11/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7857d 21h /ethmac/tags/rel_11/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7860d 22h /ethmac/tags/rel_11/
218 Typo error fixed. (When using Bist) mohor 7861d 00h /ethmac/tags/rel_11/
217 Bist supported. mohor 7861d 00h /ethmac/tags/rel_11/
216 Bist signals added. mohor 7861d 00h /ethmac/tags/rel_11/
215 Bist supported. mohor 7861d 01h /ethmac/tags/rel_11/
214 Signals for WISHBONE B3 compliant interface added. mohor 7861d 21h /ethmac/tags/rel_11/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7861d 21h /ethmac/tags/rel_11/
212 Minor $display change. mohor 7861d 21h /ethmac/tags/rel_11/
211 Bist added. mohor 7861d 21h /ethmac/tags/rel_11/
210 BIST added. mohor 7861d 21h /ethmac/tags/rel_11/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7863d 00h /ethmac/tags/rel_11/
208 Virtual Silicon RAMs moved to lib directory tadej 7878d 18h /ethmac/tags/rel_11/
207 Virtual Silicon RAM support fixed tadej 7878d 18h /ethmac/tags/rel_11/
206 Virtual Silicon RAM added to the simulation. mohor 7878d 18h /ethmac/tags/rel_11/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7878d 19h /ethmac/tags/rel_11/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7878d 19h /ethmac/tags/rel_11/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7878d 19h /ethmac/tags/rel_11/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.