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[/] [ethmac/] [tags/] [rel_11/] [bench/] [verilog/] [tb_eth_top.v] - Rev 338

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338 root 4119d 14h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
335 New directory structure. root 4176d 19h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 6479d 12h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 6552d 18h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
108 Testbench supports unaligned accesses. mohor 6678d 19h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 6744d 12h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6754d 16h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
66 Testbench fixed, code simplified, unused signals removed. mohor 6754d 22h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
51 Added separate tests for Multicast, Unicast, Broadcast billditt 6756d 09h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
49 HASH0 and HASH1 register read/write added. mohor 6758d 09h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 6764d 15h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 6824d 17h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
23 Number of addresses (wb_adr_i) minimized. mohor 6874d 18h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6874d 20h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6899d 14h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 6939d 15h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6948d 15h /ethmac/tags/rel_11/bench/verilog/tb_eth_top.v

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