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[/] [ethmac/] [tags/] [rel_11/] [rtl/] - Rev 129


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Rev Log message Author Age Path
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6619d 06h /ethmac/tags/rel_11/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6639d 05h /ethmac/tags/rel_11/rtl/
126 InvalidSymbol generation changed. mohor 6639d 05h /ethmac/tags/rel_11/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 6639d 05h /ethmac/tags/rel_11/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6641d 07h /ethmac/tags/rel_11/rtl/
120 Unused files removed. mohor 6641d 08h /ethmac/tags/rel_11/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6641d 08h /ethmac/tags/rel_11/rtl/
118 ShiftEnded synchronization changed. mohor 6644d 23h /ethmac/tags/rel_11/rtl/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6646d 07h /ethmac/tags/rel_11/rtl/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6647d 05h /ethmac/tags/rel_11/rtl/
113 RxPointer bug fixed. mohor 6653d 21h /ethmac/tags/rel_11/rtl/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6654d 10h /ethmac/tags/rel_11/rtl/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6655d 00h /ethmac/tags/rel_11/rtl/
110 m_wb_cyc_o signal released after every single transfer. mohor 6655d 03h /ethmac/tags/rel_11/rtl/
109 Comment removed. mohor 6655d 03h /ethmac/tags/rel_11/rtl/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6722d 13h /ethmac/tags/rel_11/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6731d 15h /ethmac/tags/rel_11/rtl/
104 FCS should not be included in NibbleMinFl. mohor 6733d 09h /ethmac/tags/rel_11/rtl/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6733d 09h /ethmac/tags/rel_11/rtl/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6733d 10h /ethmac/tags/rel_11/rtl/

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