OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_11/] [rtl/] - Rev 218

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
218 Typo error fixed. (When using Bist) mohor 6515d 19h /ethmac/tags/rel_11/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 6516d 16h /ethmac/tags/rel_11/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6516d 16h /ethmac/tags/rel_11/rtl
212 Minor $display change. mohor 6516d 16h /ethmac/tags/rel_11/rtl
211 Bist added. mohor 6516d 16h /ethmac/tags/rel_11/rtl
210 BIST added. mohor 6516d 16h /ethmac/tags/rel_11/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6533d 14h /ethmac/tags/rel_11/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6533d 14h /ethmac/tags/rel_11/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6536d 15h /ethmac/tags/rel_11/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6544d 18h /ethmac/tags/rel_11/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 6545d 18h /ethmac/tags/rel_11/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 6546d 19h /ethmac/tags/rel_11/rtl
165 HASH improvement needed. mohor 6546d 22h /ethmac/tags/rel_11/rtl
164 Ethernet debug registers removed. mohor 6546d 22h /ethmac/tags/rel_11/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 6547d 20h /ethmac/tags/rel_11/rtl
160 error acknowledge cycle termination added to display. mohor 6547d 20h /ethmac/tags/rel_11/rtl
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 6548d 16h /ethmac/tags/rel_11/rtl
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 6552d 14h /ethmac/tags/rel_11/rtl
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 6552d 14h /ethmac/tags/rel_11/rtl
148 Bug when last byte of destination address was not checked fixed. mohor 6552d 14h /ethmac/tags/rel_11/rtl
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 6552d 14h /ethmac/tags/rel_11/rtl
146 CarrierSenseLost status is not set when working in loopback mode. mohor 6552d 14h /ethmac/tags/rel_11/rtl
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 6552d 14h /ethmac/tags/rel_11/rtl
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 6568d 17h /ethmac/tags/rel_11/rtl
141 Syntax error fixed. mohor 6571d 10h /ethmac/tags/rel_11/rtl
140 Syntax error fixed. mohor 6571d 10h /ethmac/tags/rel_11/rtl
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 6571d 10h /ethmac/tags/rel_11/rtl
138 Synchronous reset added. mohor 6571d 11h /ethmac/tags/rel_11/rtl
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 6571d 11h /ethmac/tags/rel_11/rtl
136 Parameter ResetValue changed to capital letters. mohor 6571d 20h /ethmac/tags/rel_11/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.