OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_11/] [rtl/] - Rev 335

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
335 New directory structure. root 4106d 22h /ethmac/tags/rel_11/rtl/
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 6409d 15h /ethmac/tags/rel_11/rtl/
248 wb_rst_i is used for MIIM reset. mohor 6409d 15h /ethmac/tags/rel_11/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6412d 18h /ethmac/tags/rel_11/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6413d 13h /ethmac/tags/rel_11/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6414d 10h /ethmac/tags/rel_11/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6414d 10h /ethmac/tags/rel_11/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6414d 10h /ethmac/tags/rel_11/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6414d 10h /ethmac/tags/rel_11/rtl/
238 Defines fixed to use generic RAM by default. mohor 6426d 14h /ethmac/tags/rel_11/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6428d 19h /ethmac/tags/rel_11/rtl/
232 fpga define added. mohor 6434d 13h /ethmac/tags/rel_11/rtl/
229 case changed to casex. mohor 6440d 11h /ethmac/tags/rel_11/rtl/
227 Changed BIST scan signals. tadejm 6440d 15h /ethmac/tags/rel_11/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6440d 16h /ethmac/tags/rel_11/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6444d 16h /ethmac/tags/rel_11/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6447d 16h /ethmac/tags/rel_11/rtl/
218 Typo error fixed. (When using Bist) mohor 6447d 18h /ethmac/tags/rel_11/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 6448d 15h /ethmac/tags/rel_11/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6448d 15h /ethmac/tags/rel_11/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.