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[/] [ethmac/] [tags/] [rel_11/] [rtl/] [verilog/] - Rev 338

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338 root 5441d 06h /ethmac/tags/rel_11/rtl/verilog/
335 New directory structure. root 5498d 11h /ethmac/tags/rel_11/rtl/verilog/
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7801d 04h /ethmac/tags/rel_11/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7801d 04h /ethmac/tags/rel_11/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7804d 07h /ethmac/tags/rel_11/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7805d 03h /ethmac/tags/rel_11/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7805d 23h /ethmac/tags/rel_11/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7805d 23h /ethmac/tags/rel_11/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7805d 23h /ethmac/tags/rel_11/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7805d 23h /ethmac/tags/rel_11/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 7818d 03h /ethmac/tags/rel_11/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7820d 09h /ethmac/tags/rel_11/rtl/verilog/
232 fpga define added. mohor 7826d 03h /ethmac/tags/rel_11/rtl/verilog/
229 case changed to casex. mohor 7832d 01h /ethmac/tags/rel_11/rtl/verilog/
227 Changed BIST scan signals. tadejm 7832d 04h /ethmac/tags/rel_11/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7832d 06h /ethmac/tags/rel_11/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7836d 05h /ethmac/tags/rel_11/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7839d 06h /ethmac/tags/rel_11/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 7839d 08h /ethmac/tags/rel_11/rtl/verilog/
214 Signals for WISHBONE B3 compliant interface added. mohor 7840d 05h /ethmac/tags/rel_11/rtl/verilog/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7840d 05h /ethmac/tags/rel_11/rtl/verilog/
212 Minor $display change. mohor 7840d 05h /ethmac/tags/rel_11/rtl/verilog/
211 Bist added. mohor 7840d 05h /ethmac/tags/rel_11/rtl/verilog/
210 BIST added. mohor 7840d 05h /ethmac/tags/rel_11/rtl/verilog/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7857d 03h /ethmac/tags/rel_11/rtl/verilog/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7857d 03h /ethmac/tags/rel_11/rtl/verilog/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7860d 04h /ethmac/tags/rel_11/rtl/verilog/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7868d 07h /ethmac/tags/rel_11/rtl/verilog/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7869d 07h /ethmac/tags/rel_11/rtl/verilog/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7870d 08h /ethmac/tags/rel_11/rtl/verilog/

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