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[/] [ethmac/] [tags/] [rel_11/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

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Rev	Log message	Author	Age	Path
338		root	5459d 23h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
335	New directory structure.	root	5517d 04h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7819d 21h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7823d 00h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
238	Defines fixed to use generic RAM by default.	mohor	7836d 20h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
232	fpga define added.	mohor	7844d 19h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7858d 22h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
211	Bist added.	mohor	7858d 22h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7875d 20h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7894d 20h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7913d 16h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7915d 19h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7937d 23h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8019d 04h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8028d 06h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8064d 01h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
73	Number of interrupts changed	mohor	8084d 22h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8095d 00h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8095d 01h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v
55	Changed that were lost with last update put back to the file.	mohor	8096d 03h	/ethmac/tags/rel_11/rtl/verilog/eth_defines.v

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[/] [ethmac/] [tags/] [rel_11/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

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