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Rev Log message Author Age Path
225 Some minor changes. tadejm 7201d 10h /ethmac/tags/rel_12/
224 Signals for a wave window in Modelsim. tadejm 7201d 11h /ethmac/tags/rel_12/
223 Some code changed due to bug fixes. tadejm 7201d 11h /ethmac/tags/rel_12/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7205d 09h /ethmac/tags/rel_12/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7208d 10h /ethmac/tags/rel_12/
218 Typo error fixed. (When using Bist) mohor 7208d 12h /ethmac/tags/rel_12/
217 Bist supported. mohor 7208d 12h /ethmac/tags/rel_12/
216 Bist signals added. mohor 7208d 12h /ethmac/tags/rel_12/
215 Bist supported. mohor 7208d 13h /ethmac/tags/rel_12/
214 Signals for WISHBONE B3 compliant interface added. mohor 7209d 09h /ethmac/tags/rel_12/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7209d 09h /ethmac/tags/rel_12/
212 Minor $display change. mohor 7209d 09h /ethmac/tags/rel_12/
211 Bist added. mohor 7209d 09h /ethmac/tags/rel_12/
210 BIST added. mohor 7209d 09h /ethmac/tags/rel_12/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7210d 12h /ethmac/tags/rel_12/
208 Virtual Silicon RAMs moved to lib directory tadej 7226d 06h /ethmac/tags/rel_12/
207 Virtual Silicon RAM support fixed tadej 7226d 06h /ethmac/tags/rel_12/
206 Virtual Silicon RAM added to the simulation. mohor 7226d 06h /ethmac/tags/rel_12/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7226d 07h /ethmac/tags/rel_12/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7226d 07h /ethmac/tags/rel_12/

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