OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] - Rev 227

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
227 Changed BIST scan signals. tadejm 7194d 04h /ethmac/tags/rel_12/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7194d 06h /ethmac/tags/rel_12/
225 Some minor changes. tadejm 7194d 06h /ethmac/tags/rel_12/
224 Signals for a wave window in Modelsim. tadejm 7194d 07h /ethmac/tags/rel_12/
223 Some code changed due to bug fixes. tadejm 7194d 07h /ethmac/tags/rel_12/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7198d 05h /ethmac/tags/rel_12/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7201d 06h /ethmac/tags/rel_12/
218 Typo error fixed. (When using Bist) mohor 7201d 08h /ethmac/tags/rel_12/
217 Bist supported. mohor 7201d 08h /ethmac/tags/rel_12/
216 Bist signals added. mohor 7201d 08h /ethmac/tags/rel_12/
215 Bist supported. mohor 7201d 09h /ethmac/tags/rel_12/
214 Signals for WISHBONE B3 compliant interface added. mohor 7202d 05h /ethmac/tags/rel_12/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7202d 05h /ethmac/tags/rel_12/
212 Minor $display change. mohor 7202d 05h /ethmac/tags/rel_12/
211 Bist added. mohor 7202d 05h /ethmac/tags/rel_12/
210 BIST added. mohor 7202d 05h /ethmac/tags/rel_12/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7203d 08h /ethmac/tags/rel_12/
208 Virtual Silicon RAMs moved to lib directory tadej 7219d 02h /ethmac/tags/rel_12/
207 Virtual Silicon RAM support fixed tadej 7219d 02h /ethmac/tags/rel_12/
206 Virtual Silicon RAM added to the simulation. mohor 7219d 02h /ethmac/tags/rel_12/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7219d 03h /ethmac/tags/rel_12/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7219d 03h /ethmac/tags/rel_12/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7219d 03h /ethmac/tags/rel_12/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7222d 04h /ethmac/tags/rel_12/
201 Core size added to the document. mohor 7222d 05h /ethmac/tags/rel_12/
200 File with lower case checked in instead. mohor 7222d 05h /ethmac/tags/rel_12/
199 Datasheet name changed to lower case name. mohor 7222d 05h /ethmac/tags/rel_12/
198 Removed file. File with name in lower case will be added instead. mohor 7222d 05h /ethmac/tags/rel_12/
197 Ethernet Data Sheet. mohor 7222d 05h /ethmac/tags/rel_12/
196 Ethernet product brief. mohor 7222d 06h /ethmac/tags/rel_12/

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.