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Rev Log message Author Age Path
229 case changed to casex. mohor 7153d 23h /ethmac/tags/rel_12/
227 Changed BIST scan signals. tadejm 7154d 03h /ethmac/tags/rel_12/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7154d 04h /ethmac/tags/rel_12/
225 Some minor changes. tadejm 7154d 04h /ethmac/tags/rel_12/
224 Signals for a wave window in Modelsim. tadejm 7154d 06h /ethmac/tags/rel_12/
223 Some code changed due to bug fixes. tadejm 7154d 06h /ethmac/tags/rel_12/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7158d 04h /ethmac/tags/rel_12/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7161d 04h /ethmac/tags/rel_12/
218 Typo error fixed. (When using Bist) mohor 7161d 06h /ethmac/tags/rel_12/
217 Bist supported. mohor 7161d 06h /ethmac/tags/rel_12/
216 Bist signals added. mohor 7161d 06h /ethmac/tags/rel_12/
215 Bist supported. mohor 7161d 07h /ethmac/tags/rel_12/
214 Signals for WISHBONE B3 compliant interface added. mohor 7162d 03h /ethmac/tags/rel_12/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7162d 03h /ethmac/tags/rel_12/
212 Minor $display change. mohor 7162d 03h /ethmac/tags/rel_12/
211 Bist added. mohor 7162d 03h /ethmac/tags/rel_12/
210 BIST added. mohor 7162d 03h /ethmac/tags/rel_12/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7163d 07h /ethmac/tags/rel_12/
208 Virtual Silicon RAMs moved to lib directory tadej 7179d 00h /ethmac/tags/rel_12/
207 Virtual Silicon RAM support fixed tadej 7179d 01h /ethmac/tags/rel_12/

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