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[/] [ethmac/] [tags/] [rel_12/] - Rev 239

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Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7833d 08h /ethmac/tags/rel_12
238 Defines fixed to use generic RAM by default. mohor 7845d 12h /ethmac/tags/rel_12
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7847d 18h /ethmac/tags/rel_12
235 rev 4. mohor 7848d 08h /ethmac/tags/rel_12
234 Figure list assed to the revision 3. mohor 7848d 17h /ethmac/tags/rel_12
233 Revision 0.3 released. Some figures added. mohor 7848d 17h /ethmac/tags/rel_12
232 fpga define added. mohor 7853d 12h /ethmac/tags/rel_12
231 Description of Core Modules added (figure). mohor 7855d 13h /ethmac/tags/rel_12
229 case changed to casex. mohor 7859d 10h /ethmac/tags/rel_12
227 Changed BIST scan signals. tadejm 7859d 14h /ethmac/tags/rel_12
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7859d 15h /ethmac/tags/rel_12
225 Some minor changes. tadejm 7859d 15h /ethmac/tags/rel_12
224 Signals for a wave window in Modelsim. tadejm 7859d 17h /ethmac/tags/rel_12
223 Some code changed due to bug fixes. tadejm 7859d 17h /ethmac/tags/rel_12
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7863d 15h /ethmac/tags/rel_12
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7866d 15h /ethmac/tags/rel_12
218 Typo error fixed. (When using Bist) mohor 7866d 17h /ethmac/tags/rel_12
217 Bist supported. mohor 7866d 17h /ethmac/tags/rel_12
216 Bist signals added. mohor 7866d 17h /ethmac/tags/rel_12
215 Bist supported. mohor 7866d 18h /ethmac/tags/rel_12
214 Signals for WISHBONE B3 compliant interface added. mohor 7867d 14h /ethmac/tags/rel_12
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7867d 14h /ethmac/tags/rel_12
212 Minor $display change. mohor 7867d 14h /ethmac/tags/rel_12
211 Bist added. mohor 7867d 14h /ethmac/tags/rel_12
210 BIST added. mohor 7867d 14h /ethmac/tags/rel_12
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7868d 17h /ethmac/tags/rel_12
208 Virtual Silicon RAMs moved to lib directory tadej 7884d 11h /ethmac/tags/rel_12
207 Virtual Silicon RAM support fixed tadej 7884d 12h /ethmac/tags/rel_12
206 Virtual Silicon RAM added to the simulation. mohor 7884d 12h /ethmac/tags/rel_12
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7884d 12h /ethmac/tags/rel_12

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