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[/] [ethmac/] [tags/] [rel_12/] - Rev 242

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242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7826d 14h /ethmac/tags/rel_12/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7826d 14h /ethmac/tags/rel_12/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7826d 14h /ethmac/tags/rel_12/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7826d 14h /ethmac/tags/rel_12/
238 Defines fixed to use generic RAM by default. mohor 7838d 18h /ethmac/tags/rel_12/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7840d 23h /ethmac/tags/rel_12/
235 rev 4. mohor 7841d 14h /ethmac/tags/rel_12/
234 Figure list assed to the revision 3. mohor 7841d 22h /ethmac/tags/rel_12/
233 Revision 0.3 released. Some figures added. mohor 7841d 22h /ethmac/tags/rel_12/
232 fpga define added. mohor 7846d 17h /ethmac/tags/rel_12/
231 Description of Core Modules added (figure). mohor 7848d 19h /ethmac/tags/rel_12/
229 case changed to casex. mohor 7852d 15h /ethmac/tags/rel_12/
227 Changed BIST scan signals. tadejm 7852d 19h /ethmac/tags/rel_12/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7852d 21h /ethmac/tags/rel_12/
225 Some minor changes. tadejm 7852d 21h /ethmac/tags/rel_12/
224 Signals for a wave window in Modelsim. tadejm 7852d 22h /ethmac/tags/rel_12/
223 Some code changed due to bug fixes. tadejm 7852d 22h /ethmac/tags/rel_12/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7856d 20h /ethmac/tags/rel_12/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7859d 21h /ethmac/tags/rel_12/
218 Typo error fixed. (When using Bist) mohor 7859d 23h /ethmac/tags/rel_12/
217 Bist supported. mohor 7859d 23h /ethmac/tags/rel_12/
216 Bist signals added. mohor 7859d 23h /ethmac/tags/rel_12/
215 Bist supported. mohor 7860d 00h /ethmac/tags/rel_12/
214 Signals for WISHBONE B3 compliant interface added. mohor 7860d 19h /ethmac/tags/rel_12/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7860d 20h /ethmac/tags/rel_12/
212 Minor $display change. mohor 7860d 20h /ethmac/tags/rel_12/
211 Bist added. mohor 7860d 20h /ethmac/tags/rel_12/
210 BIST added. mohor 7860d 20h /ethmac/tags/rel_12/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7861d 23h /ethmac/tags/rel_12/
208 Virtual Silicon RAMs moved to lib directory tadej 7877d 17h /ethmac/tags/rel_12/

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