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Rev Log message Author Age Path
245 Rev 1.7. mohor 7804d 14h /ethmac/tags/rel_12
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7804d 16h /ethmac/tags/rel_12
243 Late collision is not reported any more. tadejm 7804d 22h /ethmac/tags/rel_12
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7805d 13h /ethmac/tags/rel_12
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7805d 13h /ethmac/tags/rel_12
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7805d 13h /ethmac/tags/rel_12
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7805d 13h /ethmac/tags/rel_12
238 Defines fixed to use generic RAM by default. mohor 7817d 17h /ethmac/tags/rel_12
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7819d 22h /ethmac/tags/rel_12
235 rev 4. mohor 7820d 13h /ethmac/tags/rel_12
234 Figure list assed to the revision 3. mohor 7820d 21h /ethmac/tags/rel_12
233 Revision 0.3 released. Some figures added. mohor 7820d 21h /ethmac/tags/rel_12
232 fpga define added. mohor 7825d 16h /ethmac/tags/rel_12
231 Description of Core Modules added (figure). mohor 7827d 18h /ethmac/tags/rel_12
229 case changed to casex. mohor 7831d 14h /ethmac/tags/rel_12
227 Changed BIST scan signals. tadejm 7831d 18h /ethmac/tags/rel_12
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7831d 19h /ethmac/tags/rel_12
225 Some minor changes. tadejm 7831d 20h /ethmac/tags/rel_12
224 Signals for a wave window in Modelsim. tadejm 7831d 21h /ethmac/tags/rel_12
223 Some code changed due to bug fixes. tadejm 7831d 21h /ethmac/tags/rel_12

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