OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] - Rev 250

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7800d 14h /ethmac/tags/rel_12
248 wb_rst_i is used for MIIM reset. mohor 7801d 14h /ethmac/tags/rel_12
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7804d 17h /ethmac/tags/rel_12
245 Rev 1.7. mohor 7805d 11h /ethmac/tags/rel_12
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7805d 13h /ethmac/tags/rel_12
243 Late collision is not reported any more. tadejm 7805d 18h /ethmac/tags/rel_12
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7806d 09h /ethmac/tags/rel_12
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7806d 09h /ethmac/tags/rel_12
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7806d 09h /ethmac/tags/rel_12
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7806d 09h /ethmac/tags/rel_12
238 Defines fixed to use generic RAM by default. mohor 7818d 13h /ethmac/tags/rel_12
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7820d 19h /ethmac/tags/rel_12
235 rev 4. mohor 7821d 09h /ethmac/tags/rel_12
234 Figure list assed to the revision 3. mohor 7821d 17h /ethmac/tags/rel_12
233 Revision 0.3 released. Some figures added. mohor 7821d 18h /ethmac/tags/rel_12
232 fpga define added. mohor 7826d 13h /ethmac/tags/rel_12
231 Description of Core Modules added (figure). mohor 7828d 14h /ethmac/tags/rel_12
229 case changed to casex. mohor 7832d 11h /ethmac/tags/rel_12
227 Changed BIST scan signals. tadejm 7832d 15h /ethmac/tags/rel_12
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7832d 16h /ethmac/tags/rel_12

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.