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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7843d 16h /ethmac/tags/rel_13/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7845d 21h /ethmac/tags/rel_13/
235 rev 4. mohor 7846d 12h /ethmac/tags/rel_13/
234 Figure list assed to the revision 3. mohor 7846d 20h /ethmac/tags/rel_13/
233 Revision 0.3 released. Some figures added. mohor 7846d 20h /ethmac/tags/rel_13/
232 fpga define added. mohor 7851d 15h /ethmac/tags/rel_13/
231 Description of Core Modules added (figure). mohor 7853d 17h /ethmac/tags/rel_13/
229 case changed to casex. mohor 7857d 13h /ethmac/tags/rel_13/
227 Changed BIST scan signals. tadejm 7857d 17h /ethmac/tags/rel_13/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7857d 19h /ethmac/tags/rel_13/
225 Some minor changes. tadejm 7857d 19h /ethmac/tags/rel_13/
224 Signals for a wave window in Modelsim. tadejm 7857d 20h /ethmac/tags/rel_13/
223 Some code changed due to bug fixes. tadejm 7857d 20h /ethmac/tags/rel_13/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7861d 18h /ethmac/tags/rel_13/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7864d 19h /ethmac/tags/rel_13/
218 Typo error fixed. (When using Bist) mohor 7864d 21h /ethmac/tags/rel_13/
217 Bist supported. mohor 7864d 21h /ethmac/tags/rel_13/
216 Bist signals added. mohor 7864d 21h /ethmac/tags/rel_13/
215 Bist supported. mohor 7864d 22h /ethmac/tags/rel_13/
214 Signals for WISHBONE B3 compliant interface added. mohor 7865d 17h /ethmac/tags/rel_13/

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