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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7212d 21h /ethmac/tags/rel_13/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7212d 21h /ethmac/tags/rel_13/
238 Defines fixed to use generic RAM by default. mohor 7225d 01h /ethmac/tags/rel_13/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7227d 06h /ethmac/tags/rel_13/
235 rev 4. mohor 7227d 21h /ethmac/tags/rel_13/
234 Figure list assed to the revision 3. mohor 7228d 05h /ethmac/tags/rel_13/
233 Revision 0.3 released. Some figures added. mohor 7228d 05h /ethmac/tags/rel_13/
232 fpga define added. mohor 7233d 00h /ethmac/tags/rel_13/
231 Description of Core Modules added (figure). mohor 7235d 02h /ethmac/tags/rel_13/
229 case changed to casex. mohor 7238d 22h /ethmac/tags/rel_13/
227 Changed BIST scan signals. tadejm 7239d 02h /ethmac/tags/rel_13/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7239d 03h /ethmac/tags/rel_13/
225 Some minor changes. tadejm 7239d 04h /ethmac/tags/rel_13/
224 Signals for a wave window in Modelsim. tadejm 7239d 05h /ethmac/tags/rel_13/
223 Some code changed due to bug fixes. tadejm 7239d 05h /ethmac/tags/rel_13/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7243d 03h /ethmac/tags/rel_13/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7246d 03h /ethmac/tags/rel_13/
218 Typo error fixed. (When using Bist) mohor 7246d 05h /ethmac/tags/rel_13/
217 Bist supported. mohor 7246d 06h /ethmac/tags/rel_13/
216 Bist signals added. mohor 7246d 06h /ethmac/tags/rel_13/
215 Bist supported. mohor 7246d 06h /ethmac/tags/rel_13/
214 Signals for WISHBONE B3 compliant interface added. mohor 7247d 02h /ethmac/tags/rel_13/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7247d 02h /ethmac/tags/rel_13/
212 Minor $display change. mohor 7247d 02h /ethmac/tags/rel_13/
211 Bist added. mohor 7247d 03h /ethmac/tags/rel_13/
210 BIST added. mohor 7247d 03h /ethmac/tags/rel_13/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7248d 06h /ethmac/tags/rel_13/
208 Virtual Silicon RAMs moved to lib directory tadej 7264d 00h /ethmac/tags/rel_13/
207 Virtual Silicon RAM support fixed tadej 7264d 00h /ethmac/tags/rel_13/
206 Virtual Silicon RAM added to the simulation. mohor 7264d 00h /ethmac/tags/rel_13/

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