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[/] [ethmac/] [tags/] [rel_13/] [rtl/] - Rev 255


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Rev Log message Author Age Path
255 TPauseRq synchronized to tx_clk. mohor 7258d 01h /ethmac/tags/rel_13/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7259d 07h /ethmac/tags/rel_13/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7259d 07h /ethmac/tags/rel_13/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7259d 07h /ethmac/tags/rel_13/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7260d 07h /ethmac/tags/rel_13/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7263d 11h /ethmac/tags/rel_13/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7264d 06h /ethmac/tags/rel_13/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7265d 02h /ethmac/tags/rel_13/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7265d 02h /ethmac/tags/rel_13/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7265d 03h /ethmac/tags/rel_13/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7265d 03h /ethmac/tags/rel_13/rtl/
238 Defines fixed to use generic RAM by default. mohor 7277d 07h /ethmac/tags/rel_13/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7279d 12h /ethmac/tags/rel_13/rtl/
232 fpga define added. mohor 7285d 06h /ethmac/tags/rel_13/rtl/
229 case changed to casex. mohor 7291d 04h /ethmac/tags/rel_13/rtl/
227 Changed BIST scan signals. tadejm 7291d 08h /ethmac/tags/rel_13/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7291d 09h /ethmac/tags/rel_13/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7295d 09h /ethmac/tags/rel_13/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7298d 09h /ethmac/tags/rel_13/rtl/
218 Typo error fixed. (When using Bist) mohor 7298d 11h /ethmac/tags/rel_13/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7299d 08h /ethmac/tags/rel_13/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7299d 08h /ethmac/tags/rel_13/rtl/
212 Minor $display change. mohor 7299d 08h /ethmac/tags/rel_13/rtl/
211 Bist added. mohor 7299d 08h /ethmac/tags/rel_13/rtl/
210 BIST added. mohor 7299d 08h /ethmac/tags/rel_13/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7316d 07h /ethmac/tags/rel_13/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7316d 07h /ethmac/tags/rel_13/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7319d 08h /ethmac/tags/rel_13/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7327d 10h /ethmac/tags/rel_13/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7328d 11h /ethmac/tags/rel_13/rtl/

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