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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 6850d 23h /ethmac/tags/rel_14/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6853d 05h /ethmac/tags/rel_14/
235 rev 4. mohor 6853d 19h /ethmac/tags/rel_14/
234 Figure list assed to the revision 3. mohor 6854d 03h /ethmac/tags/rel_14/
233 Revision 0.3 released. Some figures added. mohor 6854d 04h /ethmac/tags/rel_14/
232 fpga define added. mohor 6858d 23h /ethmac/tags/rel_14/
231 Description of Core Modules added (figure). mohor 6861d 00h /ethmac/tags/rel_14/
229 case changed to casex. mohor 6864d 21h /ethmac/tags/rel_14/
227 Changed BIST scan signals. tadejm 6865d 00h /ethmac/tags/rel_14/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6865d 02h /ethmac/tags/rel_14/
225 Some minor changes. tadejm 6865d 02h /ethmac/tags/rel_14/
224 Signals for a wave window in Modelsim. tadejm 6865d 03h /ethmac/tags/rel_14/
223 Some code changed due to bug fixes. tadejm 6865d 03h /ethmac/tags/rel_14/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6869d 01h /ethmac/tags/rel_14/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6872d 02h /ethmac/tags/rel_14/
218 Typo error fixed. (When using Bist) mohor 6872d 04h /ethmac/tags/rel_14/
217 Bist supported. mohor 6872d 04h /ethmac/tags/rel_14/
216 Bist signals added. mohor 6872d 04h /ethmac/tags/rel_14/
215 Bist supported. mohor 6872d 05h /ethmac/tags/rel_14/
214 Signals for WISHBONE B3 compliant interface added. mohor 6873d 01h /ethmac/tags/rel_14/

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