OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] - Rev 242

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6478d 07h /ethmac/tags/rel_14/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6478d 07h /ethmac/tags/rel_14/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6478d 07h /ethmac/tags/rel_14/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6478d 08h /ethmac/tags/rel_14/rtl/
238 Defines fixed to use generic RAM by default. mohor 6490d 12h /ethmac/tags/rel_14/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6492d 17h /ethmac/tags/rel_14/rtl/
232 fpga define added. mohor 6498d 11h /ethmac/tags/rel_14/rtl/
229 case changed to casex. mohor 6504d 09h /ethmac/tags/rel_14/rtl/
227 Changed BIST scan signals. tadejm 6504d 13h /ethmac/tags/rel_14/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6504d 14h /ethmac/tags/rel_14/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6508d 14h /ethmac/tags/rel_14/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6511d 14h /ethmac/tags/rel_14/rtl/
218 Typo error fixed. (When using Bist) mohor 6511d 16h /ethmac/tags/rel_14/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 6512d 13h /ethmac/tags/rel_14/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6512d 13h /ethmac/tags/rel_14/rtl/
212 Minor $display change. mohor 6512d 13h /ethmac/tags/rel_14/rtl/
211 Bist added. mohor 6512d 13h /ethmac/tags/rel_14/rtl/
210 BIST added. mohor 6512d 13h /ethmac/tags/rel_14/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6529d 12h /ethmac/tags/rel_14/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6529d 12h /ethmac/tags/rel_14/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.