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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 4223d 23h /ethmac/tags/rel_14/rtl/verilog/
335 New directory structure. root 4281d 04h /ethmac/tags/rel_14/rtl/verilog/
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 6520d 02h /ethmac/tags/rel_14/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6520d 02h /ethmac/tags/rel_14/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6521d 02h /ethmac/tags/rel_14/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6580d 01h /ethmac/tags/rel_14/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6580d 12h /ethmac/tags/rel_14/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 6581d 14h /ethmac/tags/rel_14/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 6581d 14h /ethmac/tags/rel_14/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 6581d 14h /ethmac/tags/rel_14/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 6581d 14h /ethmac/tags/rel_14/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6582d 20h /ethmac/tags/rel_14/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6582d 21h /ethmac/tags/rel_14/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6582d 21h /ethmac/tags/rel_14/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 6583d 21h /ethmac/tags/rel_14/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6587d 00h /ethmac/tags/rel_14/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6587d 20h /ethmac/tags/rel_14/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6588d 16h /ethmac/tags/rel_14/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6588d 16h /ethmac/tags/rel_14/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6588d 16h /ethmac/tags/rel_14/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6588d 16h /ethmac/tags/rel_14/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 6600d 20h /ethmac/tags/rel_14/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6603d 01h /ethmac/tags/rel_14/rtl/verilog/
232 fpga define added. mohor 6608d 19h /ethmac/tags/rel_14/rtl/verilog/
229 case changed to casex. mohor 6614d 17h /ethmac/tags/rel_14/rtl/verilog/
227 Changed BIST scan signals. tadejm 6614d 21h /ethmac/tags/rel_14/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6614d 23h /ethmac/tags/rel_14/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6618d 22h /ethmac/tags/rel_14/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6621d 23h /ethmac/tags/rel_14/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 6622d 01h /ethmac/tags/rel_14/rtl/verilog/

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