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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 338

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Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6586d 07h /ethmac/tags/rel_14/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 6598d 11h /ethmac/tags/rel_14/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6600d 17h /ethmac/tags/rel_14/rtl/verilog/
232 fpga define added. mohor 6606d 11h /ethmac/tags/rel_14/rtl/verilog/
229 case changed to casex. mohor 6612d 09h /ethmac/tags/rel_14/rtl/verilog/
227 Changed BIST scan signals. tadejm 6612d 13h /ethmac/tags/rel_14/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6612d 14h /ethmac/tags/rel_14/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6616d 14h /ethmac/tags/rel_14/rtl/verilog/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6619d 14h /ethmac/tags/rel_14/rtl/verilog/
218 Typo error fixed. (When using Bist) mohor 6619d 16h /ethmac/tags/rel_14/rtl/verilog/

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