OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 64

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8098d 03h /ethmac/tags/rel_14/rtl/verilog/
63 RxAbort is connected differently. mohor 8098d 06h /ethmac/tags/rel_14/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 8098d 06h /ethmac/tags/rel_14/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 8098d 08h /ethmac/tags/rel_14/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8098d 08h /ethmac/tags/rel_14/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8098d 08h /ethmac/tags/rel_14/rtl/verilog/
58 File format changed. mohor 8098d 09h /ethmac/tags/rel_14/rtl/verilog/
57 Format of the file changed a bit. mohor 8098d 09h /ethmac/tags/rel_14/rtl/verilog/
56 File format fixed a bit. mohor 8098d 09h /ethmac/tags/rel_14/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 8098d 09h /ethmac/tags/rel_14/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8098d 23h /ethmac/tags/rel_14/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8098d 23h /ethmac/tags/rel_14/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8099d 00h /ethmac/tags/rel_14/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8099d 01h /ethmac/tags/rel_14/rtl/verilog/
48 RxOverRun added to statuses. mohor 8101d 03h /ethmac/tags/rel_14/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 8101d 03h /ethmac/tags/rel_14/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8101d 03h /ethmac/tags/rel_14/rtl/verilog/
43 Tx status is written back to the BD. mohor 8102d 11h /ethmac/tags/rel_14/rtl/verilog/
42 Rx status is written back to the BD. mohor 8105d 03h /ethmac/tags/rel_14/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8107d 06h /ethmac/tags/rel_14/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.