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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

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338 root 4163d 11h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
335 New directory structure. root 4220d 16h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 6459d 14h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6522d 08h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6526d 12h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 6540d 08h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
232 fpga define added. mohor 6548d 08h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6562d 10h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
211 Bist added. mohor 6562d 10h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6579d 08h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 6598d 08h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 6617d 04h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 6619d 07h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6641d 11h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6722d 16h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6731d 18h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6767d 14h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 6788d 10h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 6798d 12h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6798d 13h /ethmac/tags/rel_14/rtl/verilog/eth_defines.v

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