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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

Rev	Log message	Author	Age	Path
55	Changed that were lost with last update put back to the file.	mohor	8103d 10h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8104d 00h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
46	HASH0 and HASH1 registers added.	mohor	8106d 03h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
42	Rx status is written back to the BD.	mohor	8110d 04h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8113d 04h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
37	Link in the header changed.	mohor	8126d 10h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8175d 05h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8175d 10h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8197d 06h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8223d 08h	/ethmac/tags/rel_14/rtl/verilog/eth_defines.v